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Rev 0; 11/07
100MHz HCSL Clock Generator
General Description
The DS4100H is a low-jitter 100MHz clock generator with a high-speed current steering logic (HCSL) output. It combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5mm by 3.2mm ceramic package. Typical phase jitter is 0.9psRMS from 12kHz to 20MHz. The device operates from a single +3.3V supply. 100MHz Output Frequency 3.3V 5% Operating Voltage HCSL Output Phase Jitter (RMS): 0.9ps Typical 39ppm Frequency Stability Over Voltage, Temperature, 10 Years of Aging Output-Enable (OE) Control Input 5mm x 3.2mm x 1.49mm Ceramic Package (LCCC) Pb Free/RoHS Compliant
Features
DS4100H
Applications
PCI Express(R)
Ordering Information
PART DS4100H+ TEMP RANGE -40C to +85C PIN-PACKAGE 10 LCCC TOP MARK 10H
+Denotes a lead-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes.
Typical Operating Circuit
TOP VIEW +
OE VCC OE OUTP PCI Express LOAD OR CONNECTOR RREF 2 RS 1 N.C.
Pin Configuration
N.C.
3.3V
6
VCC
DS4100H
5
OUTN
DS4100H
RREF GND 475 1% OUTN
RS
GND RT RT
3
*EP
4
OUTP
N.C.
N.C.
(5.00mm x 3.20mm x 1.49mm)
*EXPOSED PAD
PCI Express is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
100MHz HCSL Clock Generator DS4100H
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCC) .......................................-0.3V, +4V Continuous Power Dissipation (TA = +70C) ...................280mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ...............................-40C to +85C Soldering Temperature Profile (3 passes max) .......................................................Refer to the IPC/JEDEC J-STD-020 specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.135V to 3.465V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER Supply Voltage Supply Current Input High Voltage (OE) Input Low Voltage (OE) Input Leakage Current (OE) SYMBOL VCC ICC VIH VIL I IN (Note 1) OE = VIH, Figure 2 (Note 1) (Note 1) GND OE VCC 2.0 0 -55 CONDITIONS MIN TYP MAX 85 VCC 0.8 +10 UNITS V mA V V A
3.135 3.300 3.465
HCSL OUTPUTS (OUTP, OUTN) Output High Current Output High Voltage Output Low Voltage Output Leakage High Current Output Leakage Low Current Output Resistance Crossover Voltage Output Rise Time Output Fall Time Overshoot Undershoot Output-Enable Time to Low Level Output-Enable Time to High Level IOH VOH VOL I_LEAKH I_LEAKL RO VCROSS tR tF VOVER VUNDER t PZL t PZH 475 resistor connected between RREF and GND, VOUTN or VOUTP = 1.2V, VCC = 3.3V 5% RS = 0 , RT = 50 RS = 0 , RT = 50 (Notes 1, 2) (Notes 1, 2) -10 -10 3000 (50% x VOH) 5% 175 175 VOH + 0.2V -0.2 200 200 700 700 mV ps ps V V ns ns 12.25 13.92 15.59 612.5 696.0 779.5 0 50 +10 +10 mA mV mV A A
VOE = 0; VOUTN, VOUTP = VCC VOE = 0; VOUTN, VOUTP = 0 Measure current out of OUTN pin at V OUTN = 0.5V and 1.0V; R O = 0.5 / I0.5 - I1.0 Measure crossing voltage at OUTP and OUTN (Notes 1, 2, and 3) 20% to 80%, CL = 2pF 80% to 20%, CL = 2pF Measure overshoot voltage at OUTP and OUTN (Notes 1, 2, and 3) Measure undershoot voltage at OUTP and OUTN (Notes 1, 2, and 3) Figure 3 (Note 4) Figure 3 (Note 5)
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100MHz HCSL Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER Output Disable Time SYMBOL t PZ Figure 3 (Note 6) 100 -39 15 -30 -3 1 -7 12kHz to 20MHz 10kHz DJPN,P-P 100kHz 200kHz 1MHz 20% to 80%; CL = 2pF; Figure 2; 2 x (tR - tF) / (tR + tF) tDC Measure at OUTP and OUTN, Figure 2 (Note 9) 100Hz 1kHz Clock Output SSB Phase Noise 10kHz 100kHz 1MHz 10MHz 45 3 -90.0 -112 -115 -123 -142 -147 ps 0.9 3.0 27 15 7.0 20 55 % % ms ps +7 +30 +3 +39 CONDITIONS MIN TYP MAX 10 UNITS ns MHz ppm ppm ppm ppm/V ppm ppm ps
DS4100H
CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN Clock Output f OUT Frequency Stability Total Initial Frequency Tolerance Frequency Stability vs. Temperature Frequency Stability vs. VCC Frequency Stability vs. Load Aging (10 Years) Phase Jitter (RMS) Accumulated Deterministic Jitter Due to Power-Supply Noise (Note 8) Rise and Fall Time Mismatching Duty Cycle Oscillation Startup Time f / fO f_TOL Over temperature range, aging, load, and supply (Note 7) VCC = 3.3V, TA = +25C
f / fO | TA VCC = 3.3V f / f O | V VCC = 3.3V 5% f / fO | LOAD fAGING PJRMS 10% variation in termination resistance
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9:
All voltages are referenced to ground. With 50 load to ground on each output pin. Guaranteed by design and not production tested. tPZL is defined as the time at which VOE = 1.0V on the rising edge of OE to the time at which VOUTP or VOUTN = 0.1VOH on the falling edge of OUTP or OUTN. tPZH is defined as the time at which the voltage on the rising edge of OE is equal to 1.0V to the time at which VOUTP or VOUTN = 0.9VOH on the rising edge of VOUTP or VOUTN. tPZ is defined as the time at which VOE = 1.0V on the falling edge of OE to the time at which both VOUTP and VOUTN are less than 0.1VOH. Frequency stability is calculated as: fTOTAL = fTEMP + fVCC x 0.165 + fLOAD + fAGING. Measured with 50mVP-P sinusoidal signal on the supply from 10kHz to 1MHz. Including oscillator startup time and PLL acquisition time measured after VCC reaches 3.0V from power-on.
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100MHz HCSL Clock Generator DS4100H
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
FREQUENCY vs. TEMPERATURE
DS4100H toc01
CLOCK OUTPUT vs. SUPPLY VOLTAGE
DS4100H toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
fOUT DEVIATION FROM VCC = 3.3V (ppm)
DS4100H toc03
15 10 fOUT DEVIATION (ppm) 5 0 -5 -10 -15 -40 -20 0 20 40 60 80 TEMPERATURE (C)
1.0 fOUT DEVIATION FROM VCC = 3.3V (ppm) 0.8 0.5 0.3 0.0 -0.3 -0.5 -0.8 -1.0 3.135 3.190 3.245 3.300 VCC (V) 3.355 3.410
75.0
70.0
65.0
60.0
55.0
3.465
50.0 3.135
3.190
3.245
3.300 VCC (V)
3.355
3.410
3.465
VCC
DS4100H
COUNTER N
OE
OSCILLATOR AMPLIFIER
PFD
LOOP FILTER
VCO
COUNTER M
OUTPUT BUFFER
OUTP OUTN
RREF CURRENT ADJUST
GND
Figure 1. Functional Diagram
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100MHz HCSL Clock Generator DS4100H
OUTP OUTPUT BUFFER OUTN RT RT RT = 50 RS Z0 OUTP CL Z0 = 50, 35in LENGTH RS Z0 OUTN CL CL = 2pF RECEIVER
RS = 0 FOR TEST, 0 TO 33 TO MINIMIZE RINGING IN APPLICATION. CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY.
Figure 2. Typical Termination for HCSL Driver and Test Conditions
0.7 x VCC OE tPZH 0.3 x VCC tPZ
OUTP GND tPZL OUTN GND
Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled
Pin Description
PIN 1 2 3 4 5 6 7-10 -- NAME OE RREF GND OUTP OUTN VCC N.C. EP FUNCTION Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is enabled. If connected to logic-low, the output is three-stated. Connect a 475 Ground Positive Clock Output. Requires a series resistor and a pulldown resistor. Negative Clock Output. Requires a series resistor and a pulldown resister. +3.3V Supply Input. Device power can range from 3.135V to 3.465V. No Connection Exposed Paddle. The exposed pad must be used for thermal relief. This pad can be connected to ground. 1% resistor from RREF to ground.
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100MHz HCSL Clock Generator DS4100H
Detailed Description
The DS4100H is a low-jitter HCSL 100MHz clock generator. It combines an AT-cut crystal, an oscillator, and a low-noise PLL in a 5mm by 3.2mm ceramic package. The typical phase jitter is 0.9ps RMS from 12kHz to 20MHz. The device operates from a single +3.3V supply.
Chip Information
TRANSISTOR COUNT: 2850 SUBSTRATE CONNECTED TO GROUND PROCESS: Bipolar SiGe
PLL
The PLL generates a 1.6GHz high-speed clock signal based on the 25MHz crystal oscillator output. Clockdivider circuit M generates the output clock by scaling the VCO output frequency. Clock-divider circuit N applies a scaled version of the output clock signal to the phase/frequency detector (PFD) circuit.
Thermal Information
THETA-JA (C/W) 90
Package Information
(For the latest package outline information go to www.maxim-ic.com/DallasPackInfo.)
PACKAGE TYPE 10 LCCC DOCUMENT NO. 56-G5032-002
Output Drivers
The DS4100H is available with HCSL output buffers. When not needed, the output buffers can be disabled by driving the OE input to a logic-low. OE has an internal pullup resistor so that, if OE is left open, the outputs are enabled by default. When disabled, the output buffer goes to a high-impedance state.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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